FRC Oscillator
Note that the FRC oscillator is an internal resistor-capacitor oscillator with a non-exact output frequency. While the output can be trimmed (within limits), treat all frequency and time measurements/calculations in this section as ideal/nominal. The topic of trimming the FRC oscillator will be discussed later.
FRC without modification
The FRC oscillator has a frequency of 7.37MHz. Dividing by 2 gives a machine cycle frequency of 3.685MHz. Putting an oscilloscope on the OSC2 pin (pin 10 on the 28-pin package) indeed reveals an FCY of 3.685MHz (or a machine cycle period of 271.37ns.) These numbers are important when measuring time in an application.
The particular lines of code in the configuration_bits.h file which set this frequency and enable monitoring it the OSC2 pin are:
#pragma config FNOSC = FRC // Oscillator Mode (Internal Fast RC (FRC))
#pragma config POSCMD = NONE // Primary Oscillator Source (Primary Oscillator Disabled)
#pragma config OSCIOFNC = OFF // OSC2 Pin Function (OSC2 pin has clock out function)
The choice of FRC is made at programming time and cannot be changed without reprogramming.
FRC without modification
The FRC oscillator has a frequency of 7.37MHz. Dividing by 2 gives a machine cycle frequency of 3.685MHz. Putting an oscilloscope on the OSC2 pin (pin 10 on the 28-pin package) indeed reveals an FCY of 3.685MHz (or a machine cycle period of 271.37ns.) These numbers are important when measuring time in an application.
The particular lines of code in the configuration_bits.h file which set this frequency and enable monitoring it the OSC2 pin are:
#pragma config FNOSC = FRC // Oscillator Mode (Internal Fast RC (FRC))
#pragma config POSCMD = NONE // Primary Oscillator Source (Primary Oscillator Disabled)
#pragma config OSCIOFNC = OFF // OSC2 Pin Function (OSC2 pin has clock out function)
The choice of FRC is made at programming time and cannot be changed without reprogramming.
FRC/16
The change of one line in the aforementioned configuration bits changes the system clock and the machine cycle frequency by a factor of 16. This change slows FCY to 230.3kHz (or a machine cycle period of 4.342us. These numbered can be verified by measuring the OSC2 pin with an oscilloscope.
The particular line of code in the configuration_bits.h file which changes this frequency is:
#pragma config FNOSC = FRCDIV16 // Oscillator Mode (Internal Fast RC (FRC) divide by 16)
The choice of FRCDIV16 is made at programming time and cannot be changed without reprogramming.
The change of one line in the aforementioned configuration bits changes the system clock and the machine cycle frequency by a factor of 16. This change slows FCY to 230.3kHz (or a machine cycle period of 4.342us. These numbered can be verified by measuring the OSC2 pin with an oscilloscope.
The particular line of code in the configuration_bits.h file which changes this frequency is:
#pragma config FNOSC = FRCDIV16 // Oscillator Mode (Internal Fast RC (FRC) divide by 16)
The choice of FRCDIV16 is made at programming time and cannot be changed without reprogramming.
FRC/N
Configuring an SFR, the FRC oscillator can also be divided by a postscaler factor of 1, 2, 4, 8, 16, 32, 64, or 256. The advantage of this selection is that FCY can be changed by the program as it executes. The default postscaler factor is 1.
The particular line of code in the configuration_bits.h file which selects this frequency option is:
#pragma config FNOSC = LPRCDIVN // Oscillator Mode (Internal Fast RC (FRC) with divide by N)
The choice of LPRCDIVN is made at programming time but then the postscaler can be changed during execution.
Using this option and the default postscaler (/1) gives the identical system clock and machine cycle frequency and period as using the FRC configuration mentioned earlier. Using the postscaler value of 16 gives the identical system clock and machine cycle frequency and period as using the FRC/16 configuration mentioned earlier.
Configuring an SFR, the FRC oscillator can also be divided by a postscaler factor of 1, 2, 4, 8, 16, 32, 64, or 256. The advantage of this selection is that FCY can be changed by the program as it executes. The default postscaler factor is 1.
The particular line of code in the configuration_bits.h file which selects this frequency option is:
#pragma config FNOSC = LPRCDIVN // Oscillator Mode (Internal Fast RC (FRC) with divide by N)
The choice of LPRCDIVN is made at programming time but then the postscaler can be changed during execution.
Using this option and the default postscaler (/1) gives the identical system clock and machine cycle frequency and period as using the FRC configuration mentioned earlier. Using the postscaler value of 16 gives the identical system clock and machine cycle frequency and period as using the FRC/16 configuration mentioned earlier.
To select a specific postscalar, the FRCDIV field of the CLKDIV SFR must be written to. Simply add the appropriate line to the beginning (or other appropriate place) in your main.c.
_FRCDIV = 0; // FCY/1 (default) 3.685MHz or 271.37ns
_FRCDIV = 1; // FCY/2 1.84Mhz or 542.74ns
_FRCDIV = 2; // FCY/4 921.25kHz or 1.085us
_FRCDIV = 3; // FCY/8 460.6kHz or 2.17us
_FRCDIV = 4; // FCY/16 230.2kHz or 4.342us
_FRCDIV = 5; // FCY/32 115.1kHz or 8.69us
_FRCDIV = 6; // FCY/64 57.55kHz or 17.38us
_FRCDIV = 7; .. FCY/256 14.4kHz or 69.5us
_FRCDIV = 0; // FCY/1 (default) 3.685MHz or 271.37ns
_FRCDIV = 1; // FCY/2 1.84Mhz or 542.74ns
_FRCDIV = 2; // FCY/4 921.25kHz or 1.085us
_FRCDIV = 3; // FCY/8 460.6kHz or 2.17us
_FRCDIV = 4; // FCY/16 230.2kHz or 4.342us
_FRCDIV = 5; // FCY/32 115.1kHz or 8.69us
_FRCDIV = 6; // FCY/64 57.55kHz or 17.38us
_FRCDIV = 7; .. FCY/256 14.4kHz or 69.5us
FRC with PLL
The FRC can connect to an internal PLL to obtain higher operating speeds. To use this oscillator combination, the configuration_bits.h file needs the following modification:
#pragma config FNOSC = FRCPLL // Oscillator Mode (Internal Fast RC (FRC) w/ PLL)
The FRC can connect to an internal PLL to obtain higher operating speeds. To use this oscillator combination, the configuration_bits.h file needs the following modification:
#pragma config FNOSC = FRCPLL // Oscillator Mode (Internal Fast RC (FRC) w/ PLL)
For proper operation, the three frequency criteria shown in the top of the diagram must be met.
The registers controlling the PLL are:
The registers controlling the PLL are:
- PLLPRE: a 5-bit field in the CLKDIV register (mentioned in the FRC/N section above). This field determines the N1 parameter in the PLL block diagram and divides the source clock by a value from 2 to 33. The number loaded in PLLPRE = 2 less than the divisor N1. For example, if _PLLPRE = 8, then N1 = 10.
- PLLPOST: a 2-bit field also in the CLKDIV register. This field determines the N2 parameter in the PLL block diagram. _PLLPOST = 0 gives an N2 of 2; _PLLPOST = 1 gives an N2 of 4; and, _PLLPOST = 3 gives an N2 of 8.
- PLLDIV: a 9-bit field in the PLLFBD register. This field determines the M parameter in the PLL block diagram. _PLLDIV = 2 gives an M multiplier of 4; _PLLDIV = 48 gives an M multiplier of 50.
The relationship between these parameters is better seen with the following formulas.
Where FIN is the source oscillator.
Working backwards, it can be seen that when M = 20, and N1 = N2 = 2, that the maximum FOSC of 80MHz (FCY = 40MHz; T = 25ns) can be achieved with a 4MHz XTAL oscillator input. Since the OSC2 pin can no longer output FCY when using a XTAL, we will test these calculations with FRC which should give an FOSC of 36.85MHz (FCY = 18.425MHz: T = 54.274ns.) Under test with an oscilloscope on the OSC2 pin, this frequency is observed.
In addition to the configuration_bits.c modification mentioned earlier, the following code needs to be added to the appropriate source file to implement this example:
_PLLPRE = 0; // N1 = 2
_PLLDIV = 18; // M = 20
_PLLPOST = 0; // N2 = 2
Working backwards, it can be seen that when M = 20, and N1 = N2 = 2, that the maximum FOSC of 80MHz (FCY = 40MHz; T = 25ns) can be achieved with a 4MHz XTAL oscillator input. Since the OSC2 pin can no longer output FCY when using a XTAL, we will test these calculations with FRC which should give an FOSC of 36.85MHz (FCY = 18.425MHz: T = 54.274ns.) Under test with an oscilloscope on the OSC2 pin, this frequency is observed.
In addition to the configuration_bits.c modification mentioned earlier, the following code needs to be added to the appropriate source file to implement this example:
_PLLPRE = 0; // N1 = 2
_PLLDIV = 18; // M = 20
_PLLPOST = 0; // N2 = 2
Trimming FRC
As mentioned earlier, the FRC is a non-exact oscillator with its frequency varying slightly from one IC to the next; however, its frequency can be trimmed by approximately 880kHz (12%) faster or slower in 30kHz (0.375%) increments.
As mentioned earlier, the FRC is a non-exact oscillator with its frequency varying slightly from one IC to the next; however, its frequency can be trimmed by approximately 880kHz (12%) faster or slower in 30kHz (0.375%) increments.
If a more exacting FOSC is required, the existing FOSC must be measured to determine the current error. From this the error, a percentage error of the nominal/desired frequency must be calculated and rounded to the nearest 0.375% multiple. the number to load into the trim field is then calculated by dividing the percent error by 0.375. A positive number will increase the frequency while a negative number will decrease the frequency. The increasing trim number can be no more than +63; while the decreasing trim number can be no more than -64.
_TUN = 63; // will increase FOSC to approximately 7.4MHz.
_TUN = -64; // will decrease FOSC to approximately 7.345MHz.
_TUN = 63; // will increase FOSC to approximately 7.4MHz.
_TUN = -64; // will decrease FOSC to approximately 7.345MHz.
